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blowback: Excellent. Put me down for a couple.

Bluebirt: Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.

__patchbit__: Simultaneous with the SpaceXai testing campaign demonstrating Raptor 3 rocket motors, using available AI hardware and software to configure a Culture mind, how much mass is expected to be required for the Starship's AI?

LarsKrimi: This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHzIf those numbers are at all right it puts it in useful territory. Very much so for a first spinFor a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)

dizhn: There's also an open source Authenticator software with the same name.